In the first two articles of this series of technical tips, we talked about PCI and PCI motherboard. This is arguably the most common expansion slot on today’s computers. With some significant improvements to both of these, PCI Express is destined to replace both and offer a whole new level of computer performance.
Like the PCI Special Interest Group (PCI-SIG) AGP and PCI, the development of PCI Express can be attributed to Intel. But this time around, we’ve partnered with other big names in the industry, such as Microsoft, IBM, and Dell. Now known as PCI Express, it wasn’t the first choice for that name. Without PCI-SIG, the committee that oversees the PCI standard, 3GIO (Third Generation Input / Output) may be referencing this new format.
The development of PCI Express has its roots in the PCI and AGP standards, but it turns out that the physical connections are incompatible and this is not the only difference. The PCI standard sends data from various devices to the system over a shared bus. In the AGP standard yg-enclosure.com, a dedicated point-to-point interface sends data from the graphics card to the system. PCI Express’ approach to data transfer involves a collection of bidirectional serial connections that packetize data, similar to the behavior of network connections.
Data from PCI Express devices no longer need to be moved over a single bus or a single dedicated connection, but you can use a combination of these two-way serial connections to optimize throughput. The terms “lane” and “link” don’t sound overly technical, but they have a special meaning in PCI Express. A link is a physical connection between PCI Express devices and can consist of multiple lanes that send and receive data individually. Links can consist of 1, 2, 4, 8, 12, 16, or 32 lanes, which gives you the flexibility to allocate as many lanes as you need for a particular device. This approach has obvious advantages, and some of the more important ones include:
There is no bandwidth sharing because each lane of PCI Express communication is dedicated between the two points. The main bottleneck in PCI was that all devices shared the equivalent of one lane, and all available bandwidth had to be shared as well.
You can assign multiple lanes to a device and its performance benefits from additional speed and bandwidth. A PCI Express graphics card may be assigned 16 lanes (also known as x16), while a network adapter may be assigned only 1 lane. Each lane made available to the device is sequenced up and down in each lane where data is available to optimize throughput, increasing performance potential. This process of sending the next byte of data to the next available lane is called data striping, and obviously many lanes are suitable if you need to send large amounts of data quickly.